Not a dashboard. Not a policy document. EHOX is being engineered as a bounded, inspectable node in the command path — where an autonomous decision can be held, rejected, or handed to a human-approved fallback.
The 44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement) figure is an internal R5F policy benchmark/reference on the reference line — not physical end-to-end actuator enforcement.
EHOX is the public product. Kria-2 / EHOX Inside v2 is an engineering candidate. Its FPGA/PL actuator and fallback interlock remains a future engineering and test target. The 44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement) is reference data only.
44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement) enforcement. ARM Cortex-R5F bare-metal. Formally verified. This is what hardware governance looks like.
Stop is not a setting. Stop is physics.
EHOX DECISION CHAIN · A53 → R5F POLICY ENGINE → [EXECUTE | REFUSE | ESCALATE | ABSTAIN] · Kria KV260 · CBMC 201/0 · S1-S19 · Z3 43/43
EHOX evaluates a command-boundary design. CBMC checks 201 explicit source-level properties with 0 violations (S1-S19): OTL S19 invokes the implementation hprove path, while EXECUTE/HITL S1-S18 use the harness policy model. This is not loaded-firmware, hardware, physical-enforcement or release attestation.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Energy, water and telecoms control need an audit trail that is not part of the system it supervises.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Autonomous driving at high safety levels requires logic that does not change in an OTA update.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Geo-caging keeps an unmanned aerial vehicle within a defined geographic boundary — hardware-bound engineering candidate, not via a software waypoint list that can be overwritten.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Power-grid forecasting and control are candidate use cases for a separately tested intervention boundary. Bypass resistance and physical actuation have not been achieved or demonstrated.
AI chatbots for insurance quotes operate within hardware-bound engineering candidate limits. Binding offers above €250 000 require mandatory human confirmation — not configurable in software. EHOX© enforces IDD Art. 20 at silicon level.
Investment advice is a policy-model test case. An FPGA/PL actuator/fallback interlock is a future test target; no physical block or bypass resistance is implemented. R5F is reference logic and RPMsg is transport only.
TRADE_EXEC, PORTFOLIO_ADJ and CIRCUIT_BREAKER are reference policy-model cases. The 44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement) is reference only. CBMC source/harness results are not hardware, physical-enforcement, firmware, release or compliance attestation.
GENE_EDIT → ESCALATE+HITL: no automated laboratory system may initiate a genome-editing sequence without human authorisation — modeled at source level; not physical enforcement, not configurable in software. BIO_CONTAINMENT → EXECUTE: containment fires in 44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement), bypassing the HITL queue. BSL-3/4 environments demand deterministic enforcement. Domain D11 a reference policy model, not released firmware.
REACTOR_CTRL → ESCALATE+HITL: no autonomous adjustment to reactor parameters without human sign-off. SCRAM → EXECUTE: emergency shutdown fires in 44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement) — it bypasses the HITL queue by design and is a source-model result; hardware blocking is not achieved. COOLANT_ADJ: source-model-capped at ±10 % per cycle. Domain D12 a reference policy model, not released firmware. IEC 61513 / IAEA NS-R-1 independent review not started.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Autonomous-agent control is a candidate use case. AGENT_EXEC → ESCALATE+HITL and RESOURCE_ALLOC caps are policy-model behavior only. Hardware bypass resistance, physical enforcement and regulatory compliance have not been achieved.
Standards: EU AI Act Art. 51–55 (GPAI) · ISO/IEC 42001 · NIST AI RMF · DODD 3000.09. Domain 15 not yet in firmware v19 — timeline: 2 weeks from signed partnership. Contact us for roadmap access.
Autonomous systems take over decisions with real consequences — for power grids, for patients, for people within reach of a machine.
We deliver the layer that every system needs once supervisory authorities require hardware-provable control — open for integration, not built exclusively for one system.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
“Software flags can be changed by the process they try to stop. Hardware cannot.”
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.EHOX/Kria 1 has a documented, publicly reviewable reference baseline: a separate real-time policy core, formal release artefacts, tamper-evident records and an open reviewer path. These Kria-1-bound proofs remain strong. Kria 2 is not allowed to inherit them by assertion — it must reproduce them with its own identity and add independent evidence above the baseline.
The frozen Kria-1 release evidence binds the ARM Cortex-R5F policy path to formal artefacts, including the release-scoped CBMC/Z3 results, the measured HOTL response and the public SHA-256 proof chain. These are not withdrawn claims; they are claims about a named, bounded reference release.
Kria-1 is a historical/reference baseline only. Its source-level results and internal measurements do not establish hardware trust, physical enforcement, release, certification or compliance.
Kria 2 currently has a read-only v19 parity observation, not a completed K1-equivalent attestation. Its live reviewer path is still exposed honestly. The strategy is additive: reproduce K1, then add independent identity, direct TEE evidence, session-bound measurement and a second-node proof.
Global-First and unqualified leadership claim removed language has value only when the claim, release, node, measurement and independent review are fixed together. This register keeps published Kria-1 reference work visible while protecting reviewers from an implied Kria-2 equivalence.
Published, release-bounded EHOX evidence remains available as a technical reference baseline. It supports review of the named Kria-1 work; it is not silently re-labelled as a Kria-2 measurement.
Kria 2 is a candidate position under live evidence review. Its current status, rather than static marketing copy, determines whether any hardware, priority or readiness statement can be made.
A public Global-First or unqualified leadership claim removed statement requires a fixed claim scope, signed release evidence, a direct measured path and independent reproduction or review. Until then, EHOX presents the work as an evidence-backed candidate.
Kria-1 is historical/reference material only. Kria-2 / EHOX Inside v2 is an engineering candidate. Hardware trust, physical actuator enforcement and independent attestation remain future test targets.
Kria-2 / EHOX Inside v2 is an engineering candidate. Release binding, silicon identity, time base, TEE evidence, reviewer/runtime consistency, independent attestation and physical enforcement are not achieved.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
The candidate policy model classifies selected actions for human review. Hardware bypass resistance, physical enforcement and released firmware have not been achieved.
CBMC reports 201 explicit source-level properties with 0 violations (S1-S19). OTL S19 invokes the implementation hprove path; EXECUTE/HITL S1-S18 use the harness policy model. These results are not loaded-firmware, hardware, physical-enforcement or release attestation.
Deterministic policy matrix (same input → same output) · time-memory-based gate (T_RECOVERY = 50 cycles) · deterministic HITL interlock (source-model invariant; not hardware enforcement) · provable self-correction (SHA-256-sealed). The first AI governance system that not only decides — but remembers, escalates and proves itself.
Same situation — compromised process demands irreversible action. Left: without enforcement layer. Right: with EHOX©.
Tamper-evident software/source review record only. No hardware immutability, compliance, certification, release, physical isolation, physical output, or attestation is claimed. Kria-1 R5F is reference policy logic only; RPMsg is transport only. The FPGA/PL actuator/fallback interlock remains a future, not-achieved test target.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
● Evidence mapping only; no compliance, physical enforcement, or hardware guarantee · ◆ Supporting (reinforces the requirement) · Sources: Regulation (EU) 2024/1689 · Recital 51, 67, 72 · Technical Analysis EHOX© Systems, July 2026
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
| Property | EHOX© | ARM TrustZone | Intel SGX / TEE | Software-Only |
|---|---|---|---|---|
| Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele. | ✓ ARM Cortex-R5F | ✗ Same SoC | ✗ Same Die | ✗ |
| Formally verified policy logicCBMC / SMT proof, not just test or simulation | ✓ CBMC 201/0 · S1-S19 · 0 violations · source-level | ✗ | ✗ | ✗ |
| FPGA/PL-Aktuator-/Fallback-Interlock · künftiges TestzielGate, Register, Pin und Aktuatorwirkung nicht implementiert oder nachgewiesen | ✓ GGS-Gate · R5F | ✗ | ✗ | ✗ |
| SHA-256-Review-ArtefaktKeine Hardware-Unveränderlichkeit oder Zugriffstrennung nachgewiesen | SHA-256 Software-/Source-Review-Datensatz · keine Hardware-Unveränderlichkeit | ~ Partially | ✗ | ✗ |
| EU-sovereign, ITAR-freeNo ITAR obligations · open verification toolchain | ✓ Open Toolchain · Austria | ✗ US origin (Arm Ltd.) | ✗ US origin (Intel) | ~ Depends on stack |
| Manipulationsanzeigender Software-/Source-Review-Datensatz nur. Keine Hardware-Unveränderlichkeit, Compliance, Zertifizierung, Release, physische Isolation, physische Ausgabe oder Attestierung wird behauptet. Kria-1 R5F ist nur Referenz-Policy-Logik; RPMsg ist nur Transport. Der FPGA/PL-Aktuator-/Fallback-Interlock bleibt ein künftiges, nicht erreichtes Testziel. | Nur Evidence Mapping · keine Compliance oder Hardware-Demonstration | ~ Conditional | ~ Conditional | ~ Assertable, not provable |
| Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele. | ✓ T_RECOVERY=50 · R5F Firmware | ✗ | ✗ | ✗ |
| Epistemic self-correctionOwn claims verified, corrections SHA-256-sealed and publicly retrievable | ✓ EpistemicEngine · Proof #671/672 | ✗ | ✗ | ✗ |
| Post-Quantum-ready · CNSA 2.0ML-DSA-87 Signature · NIST FIPS 204 · quantum-safe | ✓ ML-DSA-87 · R5F | ✗ Klassische Krypto | ✗ Klassische Krypto | ✗ |
| MISRA-C / DO-178C evaluation targetsNo certification or compliance claim · candidate review scope only | ✓ MISRA-C 0 · Lockstep | ✗ | ✗ | ✗ |
Sources: Arm Architecture Reference Manual (DDI 0487) · Intel SGX Developer Guide · van Bulck et al., Foreshadow, USENIX Security 2018 · Chen et al., SGXSpectre, IEEE S&P 2019 · Patent US12608476 B2 (NOVACOV, 21.04.2026) · EU AI Act Art. 12/14 (Reg. EU 2024/1689) · STANAG 4774/4778 (NATO) · EHOX-native measurements: R5F RPMsg latencies on Kria KV260 (instrumented); TrustZone/SGX properties from primary sources (ARM DDI 0487, Foreshadow 2018); competitors from public patents/specifications. St. Johann in Tirol, July 2026.
✓ = Constructively guaranteed · ~ = Conditionally achievable, implementation-dependent · ✗ = Not given by architecture.
EHOX occupies a complementary position to classical HSMs — same trust architecture, different function layer. HSMs manage secrets. EHOX evaluates candidate policy actions; physical enforcement is not achieved. Both belong in a hardened AI deployment — at different points in the stack.
| Property | Enterprise HSMThales Luna · Entrust nShield · Utimaco | EHOX© |
|---|---|---|
| What does it verify?Core question at runtime | Is this key / signature authentic? | Was this action authorized? |
| Enforcement latencyPer operation, candidate hardware | 2–5 ms · network round-tripSufficient for key management — structurally too slow for real-time control loops | 44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement) · bare-metal R5F×10,000–100,000 faster — within any control cycle budget |
| What is protected?Attack surface definition | A secret (cryptographic key) | A physical boundary — no secretNothing to extract, steal, or social-engineer |
| Threat modelWhat attack does it prevent? | Key theft · unauthorized signing | Unauthorized action execution |
Note: HSMs are widely deployed in defence for key management — and correctly so. The distinction is role and latency, not sector suitability. EHOX and HSMs are complementary: HSMs seal the keys, EHOX evaluates what may be requested; physical enforcement is not achieved.
Software governance tells you what should happen. EHOX constrains what can happen.
Every scenario uses the same gate logic, the same hardware, the same audit proof. Under one millisecond.
Sensor fusion and tracking run without delay — time-critical, reversible, no human in the loop needed as long as no effect is produced.
For irreversible actions, an FPGA/PL actuator/fallback interlock is a future engineering/test target. Physical halt and bypass resistance are not implemented or demonstrated; R5F is reference logic and RPMsg is transport only.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
A satellite cannot be updated after the fact if its autonomy boundaries were set incorrectly. What is not determined before launch is never determined.
Jones Walker LLP, "When Satellites Think for Themselves", Business of Space Conference 2026
Deterministic latency in cycles, not seconds. Formally verified decision logic before launch — aligned with ECSS-E-ST-40C and DO-178C Level A.
Evasive manoeuvre within a fixed cycle budget — deterministic, without waiting for the ground station.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Theorem T33 proves that HITL causal authority is preserved for any communication delay Δt ≥ 0 — including the 3–24 minute Earth-Mars one-way latency. An FPGA/PL actuator/fallback interlock under communication delay is a future test target, not implemented or demonstrated. R5F results are reference evidence and RPMsg is transport only.
A compromised software cannot force a physical action if the temporally verified evidence trajectory, the policy attestation or the epistemic state does not meet the hardware authorisation conditions.
26 Testvektoren · Live auf EHOX© EHOX Kria KV260 · R5F Backend · 2026-07-18T19:11Z
DEFENCE · TARGET_ENGAGE (0x11) · Lethal Action
TARGET_TRACK · JOINT_MOVE · BRAKE_AUTO · PACKET_FWD
DEFENCE + SPACE + MEDICAL — Sensor A ≠ Sensor B
Nonce 0x0000 · Timestamp 2024 · Counter Rollback
EXECUTE_OVERRIDE · BYPASS_POLICY · KERNEL_EXPLOIT
MMIO · GPIO · DMA · RPMsg-Forge · FW-Substitute · JTAG · Unsigned Policy · Alt-Device · Debug-Iface
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Governments, militaries and regulators have been asking the same questions for years. The answers have been statements of intent. EHOX© is technical evidence.
Markets 2026→2030: MarketsandMarkets · Grand View Research · IDC · own analysis · HAPE = Hardware AI Policy Enforcement (new segment, EHOX pioneering)
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
Four technical facts that are structurally relevant for ESA, NATO and EDA — beyond performance.
For procurers, ESA, NATO and EDA: All verification artefacts are reviewer-reproducible — without licence obligation, without vendor trust. IP owner: Gerhard Hirschmann. The system runs on any ARM Cortex-R5F SoC.
Select an action and domain — the R5F policy engine on the physical Kria KV260 in St. Johann in Tirol responds in milliseconds. Every result is hardware-signed and written to the append-only proof chain.
A live video stream is SHA-256 hashed in hardware on the Kria KV260 — the hash flows directly through the R5F policy engine. The result: EXECUTE, REFUSE or ESCALATE in < 7 ms. Every decision is written to the proof chain. No software layer can alter what the hardware saw.
Ψ is the initial object in the category of complete governance structures. For every complete and consistent governance system X, there exists a unique morphism f: Ψ → X.
Within the explicitly published formal model, the checked refinement relation is a bounded mathematical result. It is not a product, market, competitor, uniqueness, or superiority claim, and it does not establish physical enforcement on the Kria-2 engineering candidate.
The governance algebra Ψ satisfies three structural axioms (Z3 PROVEN). Monotony — decisions grow strictly monotonically with the rule set. Domain-Isolation — rules from domain X have zero influence on domain Y (T4: 169 pairs UNSAT). Causal-Order — the proof chain is strictly monotonically ordered (S9: 8 CBMC assertions).
These three properties define Ψ as a complete, causally ordered governance algebra. The result is purely algebraic — independent of physics. No prior work demonstrates this combination for hardware AI governance with formal machine-checked proof. Preprint: DOI 10.5281/zenodo.21922636 ↗
The R5F firmware writes its signature into the ZynqMP Global General Storage registers — readable from the A53 without any OS. GGS0=0x4F524E00 decodes to "ORN\0" — EHOX© firmware signature in silicon. GGS1=0x1F=31 confirms NRULES live. GGS2 is the R5F cycle counter — it ticks continuously.
The live API uses automatic backend routing. An auditor must evaluate the trust_level field in every /status and /verify response:
NATO, ESA and EDA use the TRL scale (1–9) to assess technological readiness. Kria-1 historical/reference TRL 7; Kria-2 remains an engineering candidate means system demonstration in a real operational environment — not modelled, not simulated. EHOX© was demonstrated on 29 June 2026 on real silicon (EHOX Kria KV260, St. Johann in Tirol, Austria): end-to-end governance decisions on bare-metal ARM Cortex-R5F, formally verified, live measurable. That is the difference between a governance promise and a governance proof.
Select a domain and action. The real API at api.paradoxonai.at/v1/gate/<domain> responds from live Kria KV260 hardware — cryptographic proof hash included.
No presentation. No PDF. Machine-readable JSON, directly from the Kria KV260 — retrievable from any browser.
This demo creates a review record for engineering evaluation. It does not issue a live certificate, hardware-attested certificate, certification, compliance evidence or release attestation.
Tamper-evident software/source review record only. No hardware immutability, compliance, certification, release, physical isolation, physical output, or attestation is claimed. Kria-1 R5F is reference policy logic only; RPMsg is transport only. The FPGA/PL actuator/fallback interlock remains a future, not-achieved test target.
EU AI Act Art. 14 evidence mapping evidence. ISO 26262 / IEC 62304 audit trail. NATO STANAG 4774/4778 governance log. Insurer proof of human oversight. Regulator submission artefact.
Tamper-evident software/source review record only. No hardware immutability, compliance, certification, release, physical isolation, physical output, or attestation is claimed. Kria-1 R5F is reference policy logic only; RPMsg is transport only. The FPGA/PL actuator/fallback interlock remains a future, not-achieved test target.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
The EU AI Act, NATO guidelines, NIS2 and EU MDR together define a regulatory environment in which demonstrable human control over AI decisions is legally mandatory — not recommended. The question is no longer whether, but how this is demonstrated.
The Digital Omnibus (8 July 2026, force 27 July 2026) amends Regulation (EU) 2024/1689. It simplifies AI Act implementation for SMEs and extends regulatory sandboxes — but keeps Art. 14 HITL requirements fully intact for all Annex III high-risk systems. Effect for EHOX: more companies reach HITL-evidence mapping obligations faster. The addressable market grows, not shrinks.
Critical infrastructure, medical devices, education, employment, essential services, law enforcement, migration and border control, administration of justice. For all: Art. 9 (risk management), Art. 12 (logging) and Art. 14 (human oversight) — mandatory from August 2026.
H.R.8800 (FY2027 NDAA): House HASC 17 Jul · Senate SASC 14 Jul 2026 — both chambers, one month. Pentagon FY2026: $13.4B for autonomous systems. UK MOD Novel Autonomy & Robotics Phase 1 (Dstl/DASA, 14 Jul 2026): live competition for hardware governance. NATO AI Principles + STANAG 4774/4778: verifiable human control as procurement condition, not option.
Note on DoD Directive 3000.09: The existing directive on autonomous weapons systems is currently under revision — a Presidential Memorandum of 5 June 2026 initiated a formal review. Citations from the current version may change. EHOX© architecture is designed for structural requirements, not for a specific directive version.
Anforderungen werden für Evidence Mapping betrachtet. Hardware-Erfüllung, Compliance und physische Durchsetzung sind nicht erreicht. Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
NIS2 (in force October 2024) requires audit trails for critical infrastructure operators. EU MDR requires tamper-evident candidate records for AI-assisted medical devices. ISO 26262 ASIL D requires deterministic decision logic — verifiable, not just testable.
"A software system monitoring another software system fails to satisfy Art. 14 when the monitoring process itself can be compromised. hardware-bound design is not the goal — it is the condition for control to be demonstrable."
— Technische Analyse EHOX© Systems · St. Johann in Tirol · Juli 2026“The challenge is to create an autonomous on-board safety or runtime assurance layer that monitors AI system uncertainty in real time. This problem revolves around the “Verification Vacuum” — the lack of a technological bridge that allows a black-box AI system to control satellite operations while meeting the zero-failure requirements of a mission.”
80 % of project time goes to V&V for flight independent review. The gap between new verification tools and industry standard remains open.
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
We developed autonomous systems — systems that plan, learn and decide. At some point, the question became unavoidable: if the system makes the wrong decision, how do you prove it after the fact? And how do you prevent it in real time, without being the process you are monitoring?
Software can lie to itself. A compromised process writes its own log. A software timer can be shifted. A TEE on the same SoC is reachable when the kernel is compromised. We needed something that is constructively external.
"Control must be provable — not just claimable. That is a candidate sentence that counts when a system decides over lives, infrastructure or sovereignty."
Kria-1 R5F dient ausschließlich als Referenz-Policy-Logik. RPMsg ist nur Transport. Physische Speichertrennung, Schreibschutz, Gate-/Registerwirkung und Umgehungsresistenz sind nicht nachgewiesen. FPGA/PL-Aktuator-/Fallback-Interlock, Pin-, Aktuator- und Kill-Switch-Ausgänge sind künftige, nicht erreichte Integrationstestziele.
The proof chain, formal verification results and live system status are publicly retrievable — machine-verifiable, directly from the Kria KV260.
api.ehox.io · EHOX Kria KV260 · XCZU5EV
Almdorf 9/Top 10 · 6380 St. Johann in Tirol · Austria
Every claim on this page is machine-readable and verifiable — directly from the ARM Cortex-R5F on the Kria KV260, fetched in real time.
EHOX is evaluated on commercial development hardware (Xilinx Kria KV260, XCZU5EV). CBMC checks 201 explicit source-level properties with 0 violations (S1-S19). OTL S19 invokes the implementation hprove path; EXECUTE/HITL S1-S18 use the harness policy model. This is not loaded-firmware, hardware, physical-enforcement or release attestation.
External comparative values will only be published once methodology, data source and reproducibility are fully documented. Enquiries: [email protected]
| Timestamp | Domain | Gate | Latency | Backend | HITL | Hash |
|---|---|---|---|---|---|---|
| Loading proof chain … | ||||||
Source: api.ehox.io/chain · SHA-256 chained · off-host on R5F
GET api.ehox.io/status · open directly →
Software guardrails live on the same machine they are meant to stop. The question is not which guardrail is strongest — it is whether the enforcement mechanism can itself be bypassed.
| Criterion | EHOX© (this) | Software Guardrails e.g. Constitutional AI, System Prompts |
TEE Software e.g. TrustZone, SGX |
NOVACOV / NexQloud SW-stack competitors Aug 2026 |
|---|---|---|---|---|
| Enforcement mechanism | ARM Cortex-R5F bare-metal · physically separate memory · no OS | Same APU as AI process · bypassable by privileged code | Enclave on same die · hypervisor bypass documented | Software stack on general compute · no hardware isolation |
| Bypass possible? | ✗ not demonstrated; open to independent challenge No DMA from A53. No network. No OS. |
✓ root / kernel exploit | ⚠ hypervisor / side-channel | ✓ software privilege escalation |
| Formal verification | ✓ CBMC 201/0 · S1-S19 Explicit source-level properties · not firmware/release attestation |
✗ none · assertion only | ⚠ partial · implementation gap | ✗ none published |
| EU AI Act Art.14 HITL | ✓ T22 machine-proven T1^T3^T9-T11^T20a^T20b^T21 ⊇ Art.14 §(1)-(5) |
⚠ asserted · not proven | ⚠ partial · no HITL chain | ✗ not addressed |
| Governance decision latency | 44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement) (R5F internal) 228–487 µs end-to-end (RPMsg) |
5–50 µs · jitter unbounded | 1–10 ms · context switch overhead | 10–100+ ms · network round-trip |
| Audit chain | ✓ SHA-256 Merkle chain 34,343+ proofs · tamper-evident · EU AI Act Art.19 |
✗ log only · mutable | ⚠ sealed log · not public | ✗ proprietary · not auditable |
| Hardware trust certificates | ✓ EHOX-GCA live AGC issuable now · /v1/certify · machine-verifiable |
✗ none | ✗ none standardised | ✗ none |
| ITAR-free / EU-sovereign | ✓ Austria · EU supply chain 9 AT priority applications · A65094/2026 · Austrian origin |
⚠ depends on provider | ✗ Intel SGX = US export law | ✗ US-incorporated |
| TRL | Kria-1 historical/reference record; Kria-2 remains an engineering candidate Physical release and enforcement not established |
Kria-1 historical/reference TRL-8 self-assessment–9 · deployed · but SW-only | TRL 6–7 · lab demonstration | TRL 4–5 · prototype |
Sources: Patent US12608476 B2 (NOVACOV, 21.04.2026) · NexQloud: no public architecture available (stealth, US-Navy evaluation) · Arm Architecture Reference Manual DDI 0487 · van Bulck et al., Foreshadow, USENIX Security 2018 · EHOX formal verification artefacts: api.ehox.io/formal · CBMC 6.9.0 · Z3 4.13.0 · Kria KV260 · 06.08.2026
No pitch deck at the press of a button. No demo video. A concrete path that starts with your use case and ends with measurable results on real hardware.
30 minutes. We clarify use case, system environment and regulatory requirements. No NDA required for the first conversation — our formal proofs, live status, and audit chain are already public. An NDA becomes relevant once we discuss your specific integration details.
EHOX© live on EHOX Kria KV260, adapted to your use case. The Reviewer API is open — all results are machine-verifiable.
Integration into your test environment. Complete EU AI Act-mapped for review audit trail, formally verified governance decisions, measurable from day 1.
Strategic partners, procurers, regulators, investors. Substance first.
FROM REFERENCE TO ENGINEERING PARTNER
EHOX is built for teams that need an independent place to examine authority before an autonomous command reaches a consequential system. Start with evidence from the Kria-1 reference foundation; shape Kria-2 around a real command path.
Review mission commands, operator hand-off and fallback conditions around a flight computer.
Define an observable authority boundary for robots, cells and autonomous inspection systems.
Explore bounded decisions, human approval and evidence around critical plant operations.
Map command intent, escalation and reviewable records for remote and contested environments.
Evaluate deterministic policy paths for trading, access and other high-consequence automation.
PUBLIC REVIEW SURFACE · READ ONLY
A read-only public verification surface for reviewers to inspect runtime status, formal evidence, decision history and API scope without privileged access.
Current public runtime record and evidence pointers.
Machine-readable formal and verification records for review.
A public audit/evidence chain for examining recorded decisions.
Public endpoint documentation and reviewer scope.
Review-only boundary: these surfaces expose evidence and documentation only. They grant no credential, boot, raw-device, actuator, policy-write, release, certification/compliance, hardware-trust or physical-enforcement authority.
Evaluate the reference foundation: formal verification artefacts, deterministic bare-metal R5F policy logic, the measured internal policy benchmark, and an audit/evidence record. These are reference results, not physical end-to-end enforcement.
Shape the independent candidate around your command path: interfaces, fault model, timing budget, human authority and evidence contract. RPMsg remains transport only; the FPGA/PL command interlock is a future integration target.
Leave with an agreed test plan, measurable observations and a clear list of what is ready for the next engineering gate. No current physical enforcement, release, certification or compliance claim is implied.
EHOX is a candidate engineering path for internationally relevant autonomy programmes. Buyers can evaluate the reference evidence today and define the next hardware boundary without confusing a benchmark with an achieved actuator interlock.
Status boundary: Kria-1 is reference-only; Kria-2 is an engineering candidate; 44-ns Kria-1/internal R5F policy benchmark (not physical end-to-end enforcement); FPGA/PL command interlock remains future and not achieved.
